1. Field of the Invention
The present invention relates to a semiconductor device having a capacitance element of an MIM (metal-insulator-metal) structure and a method of manufacturing the same.
2. Description of Related Art
A capacitance element having a structure (MIM structure) obtained by sandwiching an insulating capacitance film between a lower electrode and an upper electrode has attracted attention as a capacitance element loaded on a system LSI for radio communication in particular, since the same has a small resistive component and can be increased in capacitance density.
While the lower electrode and the upper electrode of the capacitance element having the MIM structure are generally formed by metal films containing Al (aluminum), preparation of the lower electrode from Cu (copper) having higher conductivity than Al has been studied, in order to further reduce the resistance.
FIGS. 3(a) to 3(e) are schematic sectional views successively showing the steps of manufacturing a semiconductor device having a lower electrode made of Cu.
First, a semiconductor substrate having an interlayer insulating film 91 on the outermost surface is prepared. Then, a lower electrode 92 made of Cu is formed on the surface layer portion of the interlayer insulating film 91 by the damascene process. Thereafter a capacitance film 93 made of SiN (silicon nitride) and a metal film 94 made of TiN (titanium nitride) are laminated on the interlayer insulating film 91 in this order, as shown in FIG. 3(a).
Then, a resist pattern is formed on the metal film 94, which in turn is etched through this resist pattern as a mask. Thus, an upper electrode 95 is formed as shown in FIG. 3(b). After termination of this etching, the resist pattern is removed from the upper electrode 95 (metal film 94).
Thereafter another interlayer insulating film 96 is laminated on the capacitance film 93 and the upper electrode 95 to cover them, as shown in FIG. 3(c). Then, another resist pattern is formed on the interlayer insulating film 96, which in turn is etched through this resist pattern as a mask. Thus, through-holes 97 and 98 partially exposing the capacitance film 93 and the upper electrode 95 respectively are formed in the interlayer insulating film 96.
Then, the capacitance film 93 is etched through the interlayer insulating film 96 as a mask, whereby an opening 99 for contact with the lower electrode 92 is formed in the capacitance film 93, as shown in FIG. 3(d). At this time, not only the capacitance film 93 but also the portion of the upper electrode 95 exposed through the through-hole 98 is etched.
Thereafter a lower electrode contact plug 100 connected to the lower electrode 92 through the through-hole 97 and the opening 99 and an upper electrode contact plug 101 connected to the upper electrode 95 through the through-hole 98 are formed, whereby the semiconductor device having the structure shown in FIG. 3(e) is obtained.
In the step of forming the opening 99 in the capacitance film 93, however, the opening 99 may not be formed or the etching of the upper electrode 95 may excessively progress and the upper electrode 95 is pierced, depending on the relation between the thickness of the interlayer insulating film 96 and the time (etching time) of etching the capacitance film 93.
When the capacitance film 93 is dry-etched, for example, ions and radicals do not successfully reach the surface of the capacitance film 93 and the opening 99 is not formed in the capacitance film 93 if the thickness of the interlayer insulating film 96 is excessively large (not less than 1000 nm).
If the thickness of the capacitance film 93 is excessively small (not more than 900 nm), on the other hand, ions and radicals strongly collide with the portion of the upper electrode 95 exposed from the through-hole 98. When the etching time is set long, therefore, the upper electrode 95 is pierced, and in a worse case, the etching progresses up to the capacitance film 93. If the capacitance film 93 is etched, a pass causing capacitor leakage may be formed between the lower electrode 92 and the upper electrode 95 (upper electrode contact plug 101). When the etching time is set short, on the contrary, there is a possibility that the opening 99 cannot be formed in the capacitance film 93 and conduction between the lower electrode 92 and the lower electrode contact plug 100 cannot be attained.